Publisher's Synopsis
CMOS image sensors (CIS) have come a long way from the late 1980s and early 1990s up to where they are today. However, already since the very first developments in the field, column-level single-slope analog-to-digital converters (SS-ADC) were incorporated. The combination of an image sensor with on-chip column-level ADCs demonstrates exceptional performance as far as speed and power are concerned. It is not only the imaging array that went through a lot of new developments, so did the SS-ADC configuration. This monograph gives an overview and background of the various developments of the SS-ADCs. In Part I, some background information is given about the general CIS architecture, the CIS pixels and the noise sources present in a CIS. Part of this general technical information is used in the remaining section. Part II describes the various architectures used in a SS-ADC, starting with the most simple and earliest device described to the more complex architectures that include additional features in the ADC. After the description of the overall structure of the SS-ADCs, in Part III more details are studied about the various building blocks that are used in the SS-ADCs, such as amplifiers, comparators, ramp generators and counters. The monograph concludes with a future outlook, included in Part IV.
