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Verilog Styles for Synthesis of Digital Systems

Verilog Styles for Synthesis of Digital Systems

Paperback (10 Oct 2000)

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Publisher's Synopsis

For senior/graduate-level courses in Digital Hardware Design/Verilog.

This text is designed specifically to make the cutting-edge techniques of digital hardware design more accessible to students-e.g., synthesis from high-level specifications, and field programmable gate arrays (FPGA) for many applications. The text uses a simpler language (Verilog) and standardizes the methodology to the point where seniors and first-year graduates can get medium complex designs through to gate-level simulation in a single semester.

Book information

ISBN: 9780201618600
Publisher: Pearson Education
Imprint: Pearson
Pub date:
DEWEY: 621.392
DEWEY edition: 21
Language: English
Number of pages: 314
Weight: 481g
Height: 190mm
Width: 245mm
Spine width: 18mm