Publisher's Synopsis
A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space.
VLSI Synthesis of DSP Kernels presents the following:
- Programmable DSP-based implementation;
- Programmable processors with no dedicated hardware multiplier;
- Implementation using hardware multiplier(s) and adder(s);
- Distributed Arithmetic (DA)-based implementation;
- Residue Number System (RNS)-based implementation; and
- Multiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels.
