Routing in the Third Dimension From VLSI Chips to MCMs

Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam

Audio-visual / Multimedia Item (03 Sep 2012)

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Publisher's Synopsis

Electrical Engineering/Circuits and Electron Devices Routing in the Third Dimension From VLSI to MCMs Naveed Sherwani, Siddharth Bhingarde, and Anand Panyam A volume in the IEEE Press Series on Microelectronic Systems Stuart K. Tewksbury, Series Editor The complex computer chips of tomorrow will consist of not just one or two but several layers of metal interconnect. This makes the interconnect within a chip or a multichip module a three–dimensional problem. This book addresses the algorithmic and cell design issues in chip and MCM routing, with an emphasis on techniques for eliminating routing area. Key features include:

a wealth of algorithms
over–the–cell (OTC) routing
multi–layer VLSI/thin film MCM routing
MCM routing
how to reduce chip size
coverage of fabrication–specific issues.

This book will be of interest to CAD engineers, fabrication engineers, layout engineers, or anyone involved in integrated circuit design. It is also appropriate for use as an advanced–level text on the subject. Books of Related Interest from IEEE Press Microelectronic System Interconnections: Performance and Modeling Edited by Stuart Tewksbury 1994 Hardcover 528 pp IEEE Order No.:PC3004 ISBN 0–7803–0405–5 BiCMOS Integrated Circuit Design with Analog, Digital, and Smart Power Applications Edited by M.I. Elmasry 1994 Hardcover 528 pp IEEE Order No.:PC3467 ISBN 0–7803–0430–6 Codesign: Computer–Aided Hardware/Software Engineering Edited by Jerzy Rozenblit and Klaus Buchenreider 1995 Hardcover 464 pp IEEE Order No.:PC4028 ISBN 0–7803–1049–7

ISBN:	9780470546376
Publisher:	Wiley Blackwell
Imprint:	John Wiley & Sons, Inc.
Pub date:	03 Sep 2012
Language:	English
Number of pages:	376
Weight:	687g
Height:	234mm
Width:	161mm
Spine width:	25mm