Publisher's Synopsis
SystemVerilog provides abundant features that could overwhelm a SystemVerilog beginner. Fortunately, for a decent RTL design, only a small subset of SystemVerilog is needed. The purpose of this book is to carefully choose the right subset of SystemVerilog so that the digital designer can comfortably start their SystemVerilog design project.
In this book, FPGA application is chosen not only for its easy and quick practice but also for its wider adoption. SystemVerilog examples will be deployed broadly throughout this book for reference. For those who want to learn HDL design, this book will help them ramp up their HDL design skill quickly while avoiding the pitfalls. For those who have experience in Verilog but want to advance their knowledge to SystemVerilog, this book can be a good reference. For the VHDL designers who want to explore the features in SystemVerilog, this book can serve as a bridge since it is written in a way that the common and different concepts between VHDL and SystemVerilog are emphasized. The following are the specialties of this book:1. It provides a carefully chosen subset of SystemVerilog language for FPGA design.
2. It provides a great number of examples for easier learning and practice.
3. It shows using SystemVerilog as an efficient way for a productive verification. This book is organized as follows:
Chapter 1 first briefly describes the HDL digital design methodology. Then it describes SystemVerilog language and its syntax. Chapter 2 shows how to use SystemVerilog to describe the basic digital gates and digital hardware circuits as well as to model their behavior. It explains SytemVerilog modelling constructs: modules, procedures, interfaces, functions and packages. This chapter also covers advanced topics such as compiler directives, digital arithmetic operation and design optimization. Chapter 3 introduces the synchronous sequential digital design. It gives some example designs such as flip-flop registers, shift registers, counters and adders. The design of finite-state machine (FSM) is discussed in depth for control circuit in digital systems. The algorithmic state machine (ASM) with data path is described for data-processing digital system. It also addresses other advanced topics of timing analysis, design performance and clock-domain crossing Chapter 4 focuses on the functional simulation of digital design. It describes the general construction of test bench using SystemVerilog. It introduces the initial procedure for pre-simulation initialization, the final procedure for post-simulation processing and the task procedure for repetitive operations. It explains how to control the simulation proceeding with procedure timing control. It presents some useful system functions and tasks for math functions, file I/O and etc.. Chapter 5 addresses the FPGA design methodology. The topics covers design flow, design environment, intellectual property (IP) core usage, simulation and constraints. The FPGA design for system-on-chip (SOC) is emphasized as this type of FPGA becomes popular. The FPGA configuration options are discussed. Last but not least, it introduces helpful FPGA design practices for a successful design.
