Publisher's Synopsis
These lecture notes contain an overview of an exciting new field of research, formal methods which give the VLSI designer a firm foundation and useful tools for developing integrated circuits. Such methods allow the possibility of systematic verification in the early phases of the design process. By verifying high level descriptions of the design before concerning themselves with low level details, designers can avoid wasting time implementing circuits that would later be discarded. Obviously it can be very expensive to locate and correct errors found in the later stages of a project, especially if correcting these errors requires extensive, global changes to the design. Furthermore, the long turn-around time for circuit fabrication makes it attractive to use techniques which uncover errors at an early phase of the design. The summer school where these lectures were given was held in Denmark in June 1990, and consisted of six series of lectures, each presenting a distinct formal method.
