Publisher's Synopsis
Engineers tend to focus on logic design when developing Field Programmable Gate Arrays (FPGAs). They write good code using a Hardware Description Language (HDL) that matches an agreed-upon set of requirements. Using a Hardware Verification Language (HVL), an independent verification team ensures that the HDL code matches these requirements. Throughout the process, a suitable source control system ensures the integrity of the design and verification code. The logic design is complete.
When these tasks are complete, there is a perception that the designer can press the button in the manufacturer's design software, wait a couple of hours, download the result to the target system, and everything works. If the physical characteristics of the FPGA and the surrounding system are not considered, the design rarely works on the first try.
In FPGA design, constraints are contained in additional source files that inform the synthesis and place and route (implementation) tools on optimally creating a working FPGA using the selected device's physical properties and the physical properties of the surrounding system into account. It is important to note that the constraint file is a source file that is at least as necessary as any of the HDL files that define the logic of the system.
With FPGAs, you buy "the box" when you select the component. To be successful, you need to know how to make trade-offs between the Temporal Constraints and Spatial Constraints of "the box". The task of creating a successful FPGA design ends up being the optimization of multiple components of the system.
This text contains eight chapters. Chapter 0 describes the steps to develop good code to describe the FPGA logic. It is expected that those steps are completed before entering into the physical design phase. Chapter 1 and Chapter 2 describe Temporal Constraints and Spatial Constraints, respectively. These two chapters are the primary focus of the book. Chapter 4 describes steps used in the physical design process to achieve a successful FPGA design by optimizing the constraints and the original HDL if necessary, Chapter 5 describes good hardware design practice for FPGA Design. A description of how to stage the FPGA toolchain is shown in Chapter 6. To put things in context, Chapter 3 and Chapter 7 are case studies of how applying good design practice can lead to a successful FPGA design.
