Publisher's Synopsis
This reference for the ADSP-2100 family is an architectural and code-compatible set of 16-bit fixed-point DSP microprocessors that offer varying levels of feature integration. It offers fast, flexible arithmetic for all computations including the multiply-accumulate, extended dynamic range in computations to minimize scaling, trunkation, and slipping, program sequencing with zero-overhead looping, dual data address generation with circular buffering and bit-reversed addressing, and three-bus Harvard architecture enabling single-cycle fetch of both instruction and two data values.
