Publisher's Synopsis
The purpose of this book is to bring together developments in the design and realization of bipolar transistors. The text also covers the broader topic of the optimization of bipolar devices and processes for high-speed, digital circuits. This is achieved through the use of a quasi-analytical expression for the gate delay of an ECL logic gate. The book is intended primarily for practising engineers and scientists and for students at the postgraduate level.;In the first chapter the reader is given an overview of silicon and heterojunction technologies and is introduced to the operating principles of the bipolar transistor. A more rigorous and quantitative description of the bipolar transistor is then given in the succeeding two chapters. Chapter 2 deals with the physics of the bipolar transistor and takes the reader through the derivation of an expression for the current gain. Heavy doping effects and recombination via deep levels are covered in detail. Chapter 3 explains the modelling of bipolar transistors and includes detailed descriptions of the Ebers-Moll, Gummel-Poon and SPICE bipolar transistor models. The relationship between the forward transit time TF and the cut-off frequency fT is also explored.;Chapters 4 and 5 explain the operation of important new types of bipolar transistor. Polysilicon emitters are covered in chapter 4 from both a theoretical and a practical viewpoint. Expressions for the base current and emitter resistance of a polysilicon emitter transistor are derived and compared with results obtained on practical devices. Chapter 5 explains the theory and practice of heterojunction emitters, with particular emphasis on GaAs/GaAIAs heterojunctions.;The last two chapters deal with bipolar transistor fabrication and the optimization of bipolar processes. The key bipolar process building blocks are identified and discussed in detail in Chapter 6. These include buried layer, epitaxy, isolation, base and emitter. Examples are then given of four types of bipolar process: analogue bipolar, high-speed digital, GaAs/GaAIAs heterojunction and Bicmos. The discussion of process optimiation in chapter 7 proceeds through the medium of a quasi-analytical expression for the gate delay of an ECL logic gate in terms of all the time constants of the circuit. The application of the gate delay expression to process optimization is demonstrated by a case study involving the comparison of conventional and self-aligned bipolar processes. Finally, it is used to show how silicon and GaAs/GaAIAs transistors can be designed to give optimum switching speeds in ECL circuits.
